1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the same and in particular to semiconductor devices with an element isolating trench region wherein compressive stress of the semiconductor substrate can be alleviated in a vicinity of the trench.
2. Description of the Background Art
A conventional semiconductor device manufacturing method and a semiconductor device obtained in accordance with the manufacturing method will now be described with reference to the drawings. Referring first to FIG. 26, thermal oxidation or the like is used to form a silicon oxide film 102 on a silicon substrate 101. Chemical vapor deposition (CVD) or the like is used to form a silicon nitride film 103 on silicon oxide film 102.
Referring then to FIG. 27, patterned photoresist (not shown) is provided on silicon nitride film 103. The patterned photoresist is used as a mask to anisotropically etch silicon nitride film 103 and silicon oxide film 102 to expose a surface of silicon substrate 101. The exposed silicon substrate 101 is further etched anisotropically to form a trench 104 of 3000 to 5000 .ANG. in depth.
Referring now to FIG. 28, silicon substrate 101 is oxidized, e.g., at a temperature of 1100.degree. C. in an oxygen ambient to form a silicon oxide film 105 on the silicon substrate 101 surface exposed in trench 104. Referring then to FIG. 29, a Tetra Ethyl Ortho Silicate glass (TEOS)-based silicon oxide film 106 or the like is formed on silicon nitride film 103 to fill trench 104. Referring then to FIG. 30, chemical mechanical polishing (CMP) process or the like is applied to silicon oxide film 106 to leave silicon oxide film 106 only in trench 104.
Referring then to FIG. 31, an aqueous solution of phosphoric acid or the like is used to remove silicon nitride film 103. Referring then to FIG. 32, an aqueous solution of hydrofluoric acid or the like is used to etch silicon oxide film 102 to expose a surface of silicon substrate 101. Thus an element isolating region A completes.
Referring now to FIG. 33, thermal oxidation is used to form a silicon oxide film 107 for forming a gate oxide film on silicon substrate 101. Referring then to FIG. 34, a polysilicon film or the like (not shown) is formed on silicon oxide film 107. Photolithography and etching are then used to form a gate electrode 109 on silicon substrate 101 with a gate oxide film 107a posed therebetween.
A sidewall insulating film 110 is formed on each of both side surfaces of gate electrode 109. Gate electrode 109 and sidewall insulating film 110 are used as a mask to introduce impurity ions of a predetermined conduction type into a main surface of silicon substrate 101 to form source/drain regions 108a, 108b there. Thus a MOS transistor 112 is formed in an element forming region B. To cover MOS transistor 112, chemical vapor deposition is used to form a silicon oxide film 111 on silicon substrate 101.
Thus a main portion of a semiconductor device provided with MOS transistor 112 completes in element forming region B electrically isolated from other regions by element isolating region A
In accordance with the semiconductor device manufacturing method described above, in the FIG. 28 step a thermal process is performed to form silicon oxide film 105 on a surface of silicon substrate 101 exposed in trench 104 to electrically isolate the silicon substrate 101 surface exposed in trench 104 and a portion in a vicinity thereof that are damaged by the anisotropical etch performed in forming trench 104.
Furthermore, in the FIG. 33 step the thermal oxidation or the like used to form silicon oxide film 107 also oxidizes a portion of silicon substrate 101 located at an upper portion in trench 104.
When silicon oxide film 105, 107 or the like is grown, however, compressive stress is exerted in silicon substrate 101 substantially parallel to an interface of silicon substrate 101 and the silicon oxide film. The compressive stress is relatively intense particularly at regions S1, S2 shown in FIG. 35 and a disadvantageous crystalline defect readily results in silicon substrate 101 at regions S1, S2.
Thus, when a MOS transistor or the like is formed in element forming region B, the crystalline defect resulting in region S1 can degrade the reliability of the gate oxide film thereof and current leakage can be caused between the source/drain regions and the silicon substrate. The crystalline defect caused in region S2 can also reduce the breakdown voltage between adjacent, element forming regions Bs.